A novel Switchbox network pruning framework balancing performance with resource utilization on CGRAs

Abstract

The interconnect of a coarse-grained reconfigurable architecture is often the largest single consumer of area and power, because every channel is sized for the widest value the datapath can produce regardless of what an application actually sends over it. This work treats the width of a channel as a design variable rather than a property inherited from the datapath. A separate physical architecture description states the width, the reach and the switchbox connectivity of every individual channel, time-multiplexed converters carry a 32-bit value across a narrower channel in several cycles, and the R-Blocks toolflow is extended so that the compiler accounts for the latency a converter adds and the router never sends a value through a channel too narrow for it. Two narrowing strategies are evaluated on the same 8 × 9 shared vector fabric of 72 functional units, across two kernels and four channel widths. One narrows every unit the toolchain allows, while the other protects the schedule by leaving the register files and the control units at full width. On an FIR kernel the first removes 68.5 % of the 68 352 data wires and runs 8.41× slower, and the second removes 56.25 % and runs 3.83× slower. The two strategies do not agree across kernels, since on a GEMM kernel the aggressive one is dominated outright at 4 bits on both wires and cycles. Synthesised on GlobalFoundries 22FDX, the most heavily narrowed design is 39 % smaller and draws 27 % less power than the 32-bit baseline, although the clock network grows by up to 86 % because every converter adds registers that have to be clocked. Narrowing the whole fabric uniformly instead saves 44.6 % of system power and 58.1 % of system area. The limit on how far a network can narrow is set not by the hardware but by which units are able to declare a scheduling latency to the compiler.