Fast Emulation and Optimization of Multi-Core Heterogeneous CGRA Accelerators

Abstract

Coarse-Grained Reconfigurable Architectures (CGRAs) offer an attractive compromise be- tween the flexibility of FPGAs and the energy efficiency of ASICs. This thesis studies the integration of the Blocks/R-Blocks CGRA as a complete System-on-Chip and builds an en- vironment in which such an implementation is validated on real hardware: from a C kernel to a measurement on the board takes 15–28 minutes, against up to 8 hours in RTL simula- tion. First, the accelerator’s memory and control interfaces are migrated from the dedicated Philips DTL bus to the standard AXI-Lite and AXI-Stream protocols, enabling direct inte- gration with standard SoC infrastructure. The system is then deployed on the Zynq-7000 platform (ZC706), with a bare-metal driver handling configuration and program loading, cache coherency and execution synchronization. At a realistic DDR latency the move from DTL to AXI-Stream alone makes matrix kernels 2.6–2.9× faster, and an RTL simulation at that latency reproduces the board to within 0.2%. The memory architecture is optimized with a pipelined memory interface and a private data cache, implemented in hardware; on a matrix-vector kernel the on-board measurement shows a 1.75× speedup and a rise in com- pute efficiency from 54% to 94.5%, while shrinking the local memory from 1 MB to 32 KB cuts the BRAM requirement 4.5× at unchanged cycle count. A new functional unit, the ICU (Inter-CGRA Unit), provides direct AXI-Stream communication between CGRA cores, bypassing global memory; it is verified by a split FFT on two cores with bit-exact results; on the board, a two-layer workload split over two cores is 2.0× faster than one core, and 2.6× when each core keeps its own weights in its own cache. Finally, the platform executes five ResNet-50 convolution layers, each on its own architecture provided by the laboratory, with observability added to the platform; for three of them the output matches the reference output exactly. The on-board measurements show that the same cache changes the cycle count from 41% more cycles to 41% fewer, depending on the layer and its tiling: for a 1 × 1 convolution with a reuse distance of about 118 KB a small cache (8–64 KB) is slower than none, while with a reshaped tile the same layer gains 41% from a 32 KB cache, and 57% together with the new tile. The cost of a line fill is measured as D + L + 2 cycles and is enough to choose the configuration per layer. Board-level power cannot be distinguished from sensor noise.